Power LDMOS transistor

ABSTRACT

An LDMOS device comprises a substrate having a first conductivity type and a lightly doped epitaxial layer thereon having an upper surface. Source and drain regions of the first conductivity type are formed in the epitaxial layer along with a channel region of a second conductivity type formed therebetween. A conductive gate is formed over a gate dielectric layer. A drain contact electrically connects the drain region to the substrate, comprising a first trench formed from the upper surface of the epitaxial layer to the substrate and having a side wall along the epitaxial layer, a highly doped region of the first conductivity type formed along the side wall of the first trench, and a drain plug in the first trench adjacent the highly doped region. A source contact is provided and an insulating layer is formed between the conductive gate and the source contact.

FIELD OF THE INVENTION

The present invention relates to semiconductor structures and moreparticularly to laterally diffused MOS transistors (LDMOS), and stillmore particularly to LDMOS transistors designed for low voltage powermanagement applications.

BACKGROUND OF THE INVENTION

Power MOSFETs (metal oxide semiconductor (MOS) field effect transistors(FET)) are used as electric switches for high frequency PWM (pulse widthmodulation) applications such as voltage regulators and/or as loadswitches in power applications. When used as load switches, whereswitching times are usually long, cost, size and on-resistance of theswitches are the prevailing design considerations. When used in PWMapplications, the transistors must exhibit small power loss duringswitching, which imposes an additional requirement—small internalcapacitances—that make the MOSFET design challenging and often timesmore expensive. Special attention has been paid to the Gate-to-Drain(Cgd) capacitance, as this capacitance determines the voltage transienttime during switching and is the most important parameter affecting theswitching power loss.

Examples of prior art laterally diffused power MOSFET devices areprovided in U.S. Pat. No. 5,949,104 to D'Anna et al. and U.S. Pat. No.6,831,332 to D'Anna et al., the entirety of which are herebyincorporated by reference herein. Both devices use thick epitaxiallayers to achieve high breakdown voltage (>60V) required for the targetRF applications. To minimize the parasitic source inductance in theassembly, both devices are designed on P+ substrates leading the sourceelectrode to the back side of the die. The thick epitaxial layer and P+substrate result in a high on resistance (R_(ds,on)) of the device,which is not acceptable for power management applications. Also, bothdevice concepts lead to a stripe layout of the drain electrode. This inturn leads to a de-biasing effect known for lateral devices (voltagedrop along a stripe electrode under high current conditions) and limitsthe current handling capability of the transistor. Further, the shieldgate introduced in the U.S. Pat. No. 6,831,332 to D'Anna et al. islaterally constrained to the space between the gate and the drainelectrodes and is applicable only to a stripe layout of the drainelectrode.

There remains a need, therefore, for an LDMOS structure with improveddevice performance (R_(ds,on) and Cgd) as well as improvedmanufacturability.

SUMMARY OF THE INVENTION

An LDMOS device is provided comprising a substrate having a firstconductivity type and a lightly doped epitaxial layer thereon having anupper surface. Source and drain regions of the first conductivity typeare formed in the epitaxial layer proximate the upper surface, thesource and drain regions being spaced from one another and having achannel region of a second conductivity type formed therebetween in theepitaxial layer, the channel region extending under the source region. Aconductive gate is formed over a gate dielectric layer formed over thechannel region and partially overlapping the source and drain regions. Adrain contact electrically connects the drain region to the substrateand is spaced from the channel region, comprising a first trench formedfrom the upper surface of the epitaxial layer to the substrate andhaving a side wall along the epitaxial layer, a highly doped region ofthe first conductivity type formed along the side wall of the firsttrench, and a drain plug in the first trench adjacent the highly dopedregion. A source contact is electrically connected to the source regionand provides an electrical short between the source region and thechannel region. An insulating layer is formed between the conductivegate and the source contact.

The above and other features of the present invention will be betterunderstood from the following detailed description of the preferredembodiments of the invention that is provided in connection with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings illustrate preferred embodiments of theinvention, as well as other information pertinent to the disclosure, inwhich:

FIG. 1 is an illustration of a LDMOS transistor according to the presentinvention;

FIG. 2 is an illustration of an embodiment of a LDMOS transistor of thepresent invention having improved field plate effect;

FIG. 3 is an illustration of an embodiment of a LDMOS transistor of thepresent invention having a buffer layer for suppressing short channeleffects;

FIG. 4 is a an illustration of an embodiment of a LDMOS transistor ofFIG. 4 having a second buffer layer for improving the breakdowncharacteristics of the improved transistor;

FIG. 5 is an illustration of a region proximate to a side edge of asemiconductor substrate having the improved LDMOS transistor formedthereon; and

FIGS. 6-10 show electrical characteristics of the improved power LDMOSdevice obtained by numeric simulation.

DETAILED DESCRIPTION

As used herein, the following dopant concentrations are distinguishedusing the following notations:

(a) N++ or P++: dopant concentration>5×10¹⁹ atoms/cm³;

(b) N+ or P+: dopant concentration of 1×10¹⁸ to 5×10¹⁹ atoms/cm³;

(c) N or P: dopant concentration of 5×10¹⁶ to 1×10¹⁸ atoms/cm³;

(d) N− or P−: dopant concentration of 1×10¹⁵ to 5×10¹⁶ atoms/cm³;

(e) N−− or P−−: dopant concentration <1×10¹⁵ atoms/cm³.

FIG. 1 is an illustration of an embodiment of an improved powertransistor, more specifically and improved LDMOS transistor 10. Inexemplary applications, the transistor 10 is used as a switch in avoltage regulator of a power supply for, for example, a server ordesktop computer or in a DC/DC converter for general use.

Specifically, FIG. 1 illustrates an improved n-channel LDMOS device. Thetransistor structure 10 includes a semiconductor substrate 12, which, inthe illustrated embodiment, is preferably a highly doped (N+) siliconwafer doped with arsenic or phosphorous, for example. Highly doped (N+)substrates have lower resistances than P+ substrates, although inalternative embodiments, the substrate 12 may be P+ doped. A drainelectrode (not shown) is coupled to the bottom surface of substrate 12when the transistor structure 10 is packaged. In an exemplaryembodiment, substrate 12 has a thickness of less than or equal to about3 mils (76.2 μm), thereby providing a very low resistance contact to thedrain electrode and minimizing the contribution of the substrate to theon-resistance of the transistor. The substrate can be grinded andetched, or otherwise formed, to this desired thickness. Such processeswould typically be done toward the end of the processing of thesubstrate wafer.

A lightly doped silicon epitaxial layer 14 is formed over the substrate12 and has an upper surface 15. In certain embodiments, the epitaxiallayer 14 can have dopants of N (arsenic or phosphorous) or P (boron)dopant type and a dopant concentration of N−, N−−, P− or P−−. In oneembodiment, the epitaxial layer has a thickness between about 1.5 to 3.5μm.

The doping of the epitaxial layer is usually much lower than the dopingconcentration of the implanted source/drain regions. On the other hand,in case of devices with vertical current flow, the background doping ofthe epitaxial layer is preferably as high as possible in order to reducethe on resistance between the drain and source (R_(ds,on)) while beingjust low enough to meet the targeted breakdown voltage of thetransistor. With the present device, however, the original doping of theepitaxial layer has no effect on the resistance of the device becausecurrent flows through the vertical drain contact region 22, and thedoping concentration can be kept very low, below 5×10¹⁶ atoms/cm³, andmore preferably at or below 2×10¹⁶ atoms/cm³, for example.

A conductive gate overlies the upper surface 15 of the epitaxial layer14. In the embodiment illustrated in FIG. 1, the conductive gatecomprises a lower doped polysilicon layer 30 with an upper silicidelayer 32 formed therein or thereover by processes familiar to those inthe art. Silicide layer 32 can comprise any transition metal silicide,and in exemplary embodiments is selected from the group consisting ofTi, W and Co. The conductive gate preferably has a thickness betweenabout 0.3 to 0.6 μm and a length defined by the technology generationutilized in its fabrication, e.g., 0.8 μm, 0.5 μm, 0.35 μm. or 0.25,etc. The conductive gate is formed over a gate dielectric 36, whichpreferably comprises SiO₂ formed to a thickness between about 150 to 500Å.

Region 20 is formed completely within epitaxial layer 14 and forms anenhanced drain drift region. The enhanced drain drift region is formedabutting or at least proximate to the upper surface 15 of layer 14 andhas a dopant concentration N in the illustrated embodiment. The enhanceddrain drift region 20 increases the drain-to-source breakdown voltage ofthe LDMOS structure 10. Drain drift region 20 has a lateral dimensionbetween about 0.5 to 1.5 μm, and a depth of between about 0.2 to 0.4 μm.The region 20 preferably extends below (i.e., is overlapped by) theconductive gate between about 0.05 to 0.15 μm and is known as lightlydoped drain (LDD) structure in the literature, such as U.S. Pat. No.5,907,173 to Kwon et al., the entirety of which is hereby incorporatedby reference herein.

The LDMOS structure 10 also includes a source implant region 18 having aconductivity N+ spaced from the enhanced drain drift region 20. Sourceregion 18 extends laterally between about 0.5 to 0.8 μm, has a depthbetween about 0.15 to 0.3 μm and also partially underlies the conductivegate between about 0.05 to 0.15 μm. A body region 16 having P-typedopants and having a conductivity of P concentration is formed inepitaxial layer 14 and has a subregion between the source 18 andenhanced drain region 20, forming a channel region therebetween. Thebody region 16 includes source contact region 18 and body contact region26. In exemplary embodiments, the body region 16 is formed to a depth ofbetween about 0.5 to 1.0 μm and horizontal length between about 0.8 to1.5 μm.

The body contact region 26 has a dopant concentration P++greater thanthe concentration of the body region 16. In one embodiment, the bodycontact region 26 is formed at the base of a shallow trench region 19and has a lateral dimension between about 0.1 to 0.3 μm and is formed toa depth between about 0.1 to 0.3 μm. The body contact region 26 providesfor a low resistance contact between the source metal layer 28(described in more detail below) and the body region 16. Under blockingcondition where the voltage applied to the drain electrode results in areverse bias of the body-to-drain PN-junction, the depletion layer orregion is “squeezed” in the vertical direction between the contactimplant 26 and the doping gradient from the substrate 12. The reducedwidth of the depletion layer results in a lower source-drain breakdownvoltage, localizing the place where the breakdown occurs beneath thecontact implant. This, in turn, defines the path for the currentgenerated during the avalanche condition, i.e., when the electric fieldat the body-to-drain PN-junction is so high that it leads to ageneration of minority carriers by impact ionization.

A deep trench region 25 (shown filled with a plug 24) is formed adjacentenhanced drain drift region 20 and spaced from the conductive gate. Thetrench 25 is formed between the upper surface 15 of the epitaxial layer14 to the upper surface of the substrate 12. The trench enables theformation of vertical drain contact region 22 adjacent the sidewalls oftrench region 25, which provides a low resistance path between theenhanced drain drift region 20 and substrate 12 (and thus the drainelectrode (not shown)). In the n-channel embodiment shown in FIG. 1, thedrain contact 22 has a dopant concentration N+ or higher and is formedby low angle implantation while trench 25 is open. Trench 25 is thenfilled with a conductive material (e.g., tungsten or doped polysilicon)or insulative material (e.g., Si_(x)O_(y)) to form plug 24. In oneembodiment, drain contact 22 has a horizontal dimension into epitaxiallayer 14 in the amount of about 0.4 to 0.8 μm. In other embodiments, theepitaxial layer is very thin (e.g., 1.5 μm) and there is no need to etchthe trench. The drain contact is created by a diffused region(s) offirst conductivity type, created by multiple implants and extending fromthe surface to the substrate. There is no need for a drain plug in thisembodiment, as no deep trench 25 is formed.

The device 10 also includes an insulating layer 34 formed over thesource implant region 15, over the conductive gate sidewalls and itsupper surface, as well as over the enhanced drain drift region 20 andcontact plug 24. The insulating layer preferably comprises SiO₂ orSiO_(x)N_(y). It should be understood, however, that insulating layer 34can comprise several layers of insulating materials collectively forminginsulating layer 34. Insulating layer 34 is preferably formed to athickness of at least 0.03 μm on the sidewalls of the conductive gateand at least 0.05 μm on the top surface of the conductive gate. In anexemplary embodiment, insulating layer 34 is formed to a thicknessbetween about 0.05-0.15 μm over the drain region 20. The insulatinglayer insulates the drain and gate regions from the source contact layer28, described below.

As is shown in FIG. 1, device 10 also includes a source contact layer28, which preferably comprises conductive material selected from thegroup consisting of Al, Ti/Al, Ti/TiN/Al or W blanket deposited over thedevice such as by CVD (chemical vapor deposition) or sputtering. Thesource contact layer 28 is deposited to fill shallow trench 19 toprovide a contact between a source electrode (not shown) and the sourceimplant 18 as well as provide a short between the source and bodyregions 18, 16. Source layer 28 extends over insulation layer 34, overthe conductive gate and over the drain implant region 20 and drain plug24. In one embodiment, the source metal layer 28 has a thickness definedbetween the upper surface 15 of the epitaxial layer 14 and its uppersurface 29 between about 1.0 to 5.0 μm.

When the device 10 is turned “on,” the conduction current flows throughthe source metal 28, laterally through the channel underneath the gateto the drain contact region 20 and then vertically along the vertical,highly doped drain contact 22 though the substrate 12 to the drainelectrode (not shown) placed at the bottom side of the device 10.

The source contact structure 28 of FIG. 1 provides several advantages.First, a single layer of metal can serve as a source contact and ashield electrode, which shields the conductive gate from the draincontact 22 and reduces the capacitance between the gate and drain (Cgd).There is no need to form a separate shield gate nor is there a need toseparately connect the shield gate to the source. The manufacturabilityof the device is thereby greatly improved.

Further, the drain-source resistance (Rsd) is optimized by the use of anN+ substrate. As those in the art will recognize, n-channel devicesdesigned for RF applications are typically formed on P+ substratesbecause it is important to have the source electrode at ground potentialat the bottom of the die. Although n-channel devices may be preferredfor their lower channel resistance compared to p-channel devices, thep-doped substrates of the prior art provide much higher resistances thann-substrates, often 2 to 3 times higher. The present device 10, however,provides an n-channel device on a low resistance n-doped substrate.

An exemplary method of forming device 10 is now described. Certaindetails which will be readily apparent to those in the art areeliminated so as to avoid obscuring the present invention. Substrate 12is provided with a pre-defined N+ dopant concentration. Epitaxial layer14 having dopant concentration of N− or P− is next formed over the uppersurface of the substrate 12. A first trench is etched through theepitaxial layer after depositing and patterning of a thin oxide layerused as a dedicated drain contact mask. The side walls of the trench areN+ doped with a 7 degree implant of a suitable dopant, preferablyPhosphorous or Arsenic, to form the drain contact regions. The firsttrench is filled with a material to form the drain plug. In oneembodiment, the trench is filled with N+ doped polysilicon. Next, thepolysilicon is etched back to a level slightly below the surface of theepitaxial layer and the oxide mask is removed.

After forming the drain contact and plug regions in the epitaxial layer14, a thin gate oxide layer is formed over the upper surface 15 of theepitaxial layer. Next, a layer of polysilicon is deposited and etched toform a polysilicon gate. Silicide layer 32 is then formed using the wellknow salicide process or a silicide layer is deposited over thepolysilicon layer and etched therewith to form the stackedpolysilicon/silicide structure shown in FIG. 1. Following the formationof silicide layer 32, P-body or N-enhanced drift regions are formed bymasked implantation of respective dopants and thermal diffusion steps.The side spacers adjacent the conductive gate can be separately formedusing a known side wall spacer process if necessary. For example, anoxide layer can be deposited and etched back with an anisotropicreactive ion etch (RIE). The N+ source region is formed by implantationof Arsenic using a patterned photoresist as a mask.

Next, shallow trench 19 is patterned and etched to the desired depth,followed by formation of implant region 26. An oxide layer 34 isdeposited over the upper surface 15 and conductive gate to the desiredthickness. Finally, a metal layer is deposited over the entire structureto form source contact 28. The original substrate is then thinned to adesired thickness and a backside metal (not shown) is deposited to fromthe drain electrode. The device is then packaged and tested.

FIG. 2 illustrates a second embodiment 10A of the improved LDMOS device.The device 10A is identical in all respects to the device 10 of FIG. 1,and like features are identified by like reference numbers, except formodified insulation layer 34A and modified source metal layer 28A. Itshould be understood that source metal layer 28A is modified only in somuch as it is deposited over modified insulation layer 34A. In theregions proximate to the drain implant region 20 and drain plug 24,modified insulation layer 34A has two thicknesses. More specifically,modified insulation layer 34A has a thicker region designated generallyat 35 formed over drain plug 24 and parts of drain region 20 and athinner portion 37 formed over drain region 20 and between the thickerportion 35 and the gate. In one embodiment, the length of the thin oxideregion 37 amounts to about ½ to ¾ of the distance between the gate 30and the drain plug 24. In an exemplary embodiment, the thickness ofthinner portion 37 is between about 0.05-0.15 μm and the thickness ofthe thicker portion 35 is between about 0.2-0.5 μm. The improvedinsulation layer 34A can be formed first by etching a thicker, oxidelayer deposited after the formation of the drain plug region. The thinoxide region 37 is deposited after gate formation and its thickness isadds to the final thickness of the region 34A, including portion 35.

In the embodiment of FIG. 2, not only does the source metal layer 28Aprovide a contact to the source and body regions and a shield betweenthe gate and the drain contact, it provides for better optimization ofthe field plate effect. The thin oxide region 37 makes the field plateeffect very effective at the gate corner by pushing the depletion layeraway from the PN-junction between the body region 16 and the drain 20.If the thin oxide were to extend laterally to cover all of the drainregion 20 and the drain plug 24, a high electric field peak would belocated at the N−N+ drain contact corner. Making the oxide thicker at 35relieves the electric field between the source metal and the draincontact region 22. The doping and the length of the drain regionunderneath the field plate, the position of the oxide step and the oxidethickness can be optimized for a given breakdown voltage target. As anexample, the design of this portion of the transistor can be as followsfor a target breakdown voltage of 20V:

total gate to drain plug distance 0.8-1.2 μm;

length of the thin oxide region 0.5-0.8 μm;

thickness of the thin oxide region 0.06-0.1 μm;

thickness of the thick oxide region 0.2-0.3 μm; and

the dose and the energy of the LDD implant 5×10¹² to 7×10¹² atoms/cm²and 80 to 150 keV.

FIG. 3 illustrates another alternative embodiment 10B of the LDMOSdevice of either FIG. 1 or FIG. 2. The device 10B of FIG. 3 is identicalto the devices 10, 10A except in the following respects: the depth ofbody implant region 16B is reduced and first buffer region 38 isprovided between body region 16B and substrate 12. In an exemplaryembodiment, first buffer region 38 comprises a layer of silicon dopedwith p-dopants at a concentration equal to or greater than the dopantconcentration of the body region 16B. The buffer layer 38 abuts thesidewalls of vertical drain contact 22, and is preferably formed to athickness between about 0.3 to 0.6 μm. In one embodiment, the bufferlayer 38 is formed by deep implantation of Boron into the epitaxiallayer 14. In the embodiment 10B from FIG. 3, this deep implantation isperformed after the patterning of the thick oxide 34A, before theformation of the gate. The buffer layer 38 serves to suppress the welldocumented short channel effects by helping to ensure that the depletionregion does not reach too far into the channel.

In the embodiment of FIG. 3, the breakdown location is still dependentin part on the thickness of epitaxial layer 14 and on the dopingconcentration of the substrate 12. Turning to the embodiment 10C of FIG.4, the buffer layer 38 is replaced with thinner p-buffer layer 38C andsecond buffer layer 40 having dopant concentration N. In this doubledeep implant buffer construction, the breakdown location isadvantageously located at or around the P-N junction between bufferlayer 38C and buffer layer 40, making the breakdown location largelyindependent of the thickness of the epitaxial layer and the dopantconcentration of the substrate 12. The deep implantation of N dopants(preferably Phosphorous) to form the second buffer layer 40 is performedat the beginning of the process flow, after the deposition of theepitaxial layer 14.

FIG. 5 illustrates the edge termination at the peripheral cells of thedevice of FIG. 2, so no gate is shown. The structure of the edgetermination is important from a design perspective because it closes theP-N junction in a manner assuring the target breakdown voltage. Theillustrated edge termination region surrounds the active area of thetransistor(s) created by P-well 16. It should be understood that asingle die can have a plurality of identical transistor cells asdescribed above fabricated in parallel and operating as a singletransistor in, for example, a power switch. The source metal 28A extendsbeyond the P-well 16 and acts as a field plate (which affects thebreakdown voltage in this region of the device), as described above inconnection with FIG. 2. The insulation layer underneath the field plateportion of layer 28A (again illustrated by reference number 35) has athickness between about 0.2-0.5 μm like thicker oxide portion 35 ofinsulation layer 34A shown in FIGS. 2-4. The drain plug 24 is formed at,or proximate to, the edge of the singulated die having the transistorformed therein, i.e., the die is singulated from adjacent dies on awafer at or proximate to the drain plug 24. The edge termination regionends with drain plug 24 separating the transistor from the edge of thesingulated die. This illustrated structure is the natural consequence ofthe formation of the structure of FIG. 2.

In a preferred embodiment, the background doping of the epitaxial layeris 1×10¹⁶ atoms/cm³, the P-well 16 is formed by overlapping deep buffer38 and body 16 implantations and the distance between the P-well and thedrain plug is 1.5 μm. This edge termination can support breakdownvoltages higher than 35V.

In an exemplary application, the improved power LDMOS device isfabricated in parallel with a plurality of other similarly structureddevices and packaged for use as a power transistor in, for example, aDC/DC voltage regulator.

FIGS. 6-10 show electrical characteristics obtained by numericsimulation of a 20V device 10 of FIG. 4 with an active area of 1 mm²designed for a maximum breakdown voltage of 20V and a maximum allowedsource-to-gate voltage of 12V, with a gate thickness of 300 Å. FIG. 6shows drain current as a function of the drain voltage at Vgs equal to2.0, 2.5, 3.0, 4.0 and 5.0 volts. The flat Ids curve in saturationregion (Vds >1 V) shows the transistor is free of short channel effects.

FIG. 7 shows the resistance of a device with an active area of 1 mm²calculated as a function of the gate voltage for the drain voltage of0.1 V. It can be seen that the resistance predicted for Vgs equal to4.5V is about 13 mΩ*mm², whereas the resistance of similar devices inthe art is higher than 20 mΩ*mm².

FIG. 8 shows the drain current as a function of the gate voltage for adrain voltage of 5V. It can be seen that the threshold voltage of thetransistor is kept at a low value below 1.5V, which is advantageous forpower applications. In contrast, modern power MOSFETs with short channellengths usually result in a much higher threshold voltage of more than2.2V to keep the device free of short channel effects.

FIG. 9 shows the capacitances Ciss, Coss and Crss as a function of thedrain voltage, where Ciss is the input capacitance (Cgs+Cgd), Coss isthe output capacitance (Cds+Cdg) and Crss is the feedback capacitance(Cdg). Cdg is very close to Cgd, depending on to what terminals thesource signals are applied and at what terminals the response signalsare measured. Generally speaking, the proposed device has smallercapacitances than the commercially available products. Particularly, thefeedback capacitance Crss (approximately equal to Cgd) is smaller by afactor of 5 than similar existing power MOSFETS.

Finally, FIG. 10 shows a gate charge curve. It can be seen from thecurve that that a gate voltage of 5V can be reached by charging the gatewith only 2.2 nC/mm². This is a very low charge providing an acceptedfigure of merit of Rds(Vgs=10V)*Qg(VS=5V) of 22 mΩ*nC, whereas thesimilar devices in the art result in values higher than 50 mΩ*nC.

As set forth above, an improved power LDMOS device is provided having ann-channel transistor formed over a low resistance N-substrate. Thedevice exhibits low on-resistance (R_(ds-on)) by lowering the resistivecontribution of the substrate and low Cgd capacitance by minimizing theelectrostatic coupling between the gate and drain electrodes. Inembodiments, the source contact extends over gate and drain regions,thereby providing a high current capability.

Although the invention has been described in terms of exemplaryembodiments, it is not limited thereto. Rather, the appended claimsshould be construed broadly to include other variants and embodiments ofthe invention that may be made by those skilled in the art withoutdeparting from the scope and range of equivalents of the invention.

1. A lateral metal-oxide-semiconductor transistor device comprising: asubstrate having a first conductivity type having a lightly dopedepitaxial layer thereon having an upper surface; source and drainregions of the first conductivity type formed in the epitaxial layerproximate the upper surface, said source and drain regions being spacedfrom one another and having a channel region of a second conductivitytype formed therebetween in said epitaxial layer, said channel regionextending under said source region; a conductive gate formed over a gatedielectric layer formed over said channel region and partiallyoverlapping said source and drain regions; a drain contact electricallyconnecting said drain region to said substrate and spaced from saidchannel region comprising: a first trench formed from the upper surfaceof said epitaxial layer to said substrate and having a side wall alongsaid epitaxial layer; a highly doped region of said first conductivitytype formed along said side wall of the first trench; and a drain plugin said first trench adjacent said highly doped region; a source contactelectrically connected to said source region and providing an electricalshort between the source region and the channel region; and aninsulating layer formed between said conductive gate and said sourcecontact.
 2. The device of claim 1, further comprising a second trenchformed adjacent said source and channel regions and extending into saidchannel region, wherein said insulating layer extends along sidewalls ofsaid conductive gate, over said conductive gate and over said drainregion, and wherein said source contact comprises a layer of conductivematerial deposited in said second trench and over said insulating layer.3. The device of claim 2, wherein said layer of conductive material hasa generally planar upper surface and covers said conductive gate anddrain region.
 4. The device of claim 2, wherein said insulating layerhas a thickness between about 0.05 to 0.15 μm over said drain region,whereby said source metal shields said conductive gate from said draincontact.
 5. The device of claim 2, wherein said insulating layercomprises a first portion over said drain region and a second portionover said drain plug, said second portion being thicker than said firstportion.
 6. The device of claim 5, wherein said first portion has athickness between about 0.05 to 0.15 μm and said second portion has athickness between about 0.2 to 0.5 μm.
 7. The device of claim 2, whereinsaid insulating layer has a thickness along sidewalls of said conductivegate greater than about 0.03 μm and a thickness over a top surface ofsaid conductive gate greater than about 0.05 μm.
 8. The device of claim1, further comprising a first buffer region of said second conductivitytype formed between said substrate and said channel region, said firstbuffer having a conductivity greater than or equal to the conductivityof said channel region.
 9. The device of claim 8, further comprising asecond buffer region of said first conductivity type formed between saidfirst buffer region and said substrate.
 10. The device of claim 9,wherein said first and second buffer regions are implant regions formedin said epitaxial layer.
 11. The device of claim 2 further comprising ahighly doped region of said second conductivity type formed in saidchannel region proximate a bottom of said second trench.
 12. The deviceof claim 1, wherein said drain plug comprises a conductive material. 13.The device of claim 1, wherein said drain plug comprises an insulatingmaterial.
 14. The device of claim 2, further comprising an edgetermination region surrounding the active area of said transistor andseparating said transistor from an edge of a die having said transistorformed thereon, said edge termination region comprising a well region ofthe second conductivity type formed in said epitaxial layer, whereinsaid layer of conductive material extends beyond said well region andover said insulating layer; and wherein said drain plug is formed at orproximate to said edge of the die.
 15. The device of claim 1, whereinsaid substrate has a thickness of less than or about 76 μm.
 16. Thedevice of claim 1, wherein said first conductivity type is Nconductivity type and said substrate has a highly doped concentration.17. A lateral metal-oxide-semiconductor transistor device comprising: ahighly doped semiconductor substrate having a N conductivity type andhaving a lightly doped epitaxial layer thereon having an upper surface;source and drain regions of the N conductivity type formed in theepitaxial layer proximate the upper surface, said source and drainregions being spaced from one another and having a channel region of a Pconductivity type formed therebetween in said epitaxial layer, saidchannel region extending under said source region; a conductive gateformed over a gate dielectric layer formed over said channel region andpartially overlapping said source and drain regions; at least one bufferlayer having a dopant concentration equal to or greater than saidchannel region formed between said channel region and said substrate; adrain contact electrically connecting said drain region to saidsubstrate and spaced from said channel region comprising: a first trenchformed from the upper surface of said epitaxial layer to said substrateand having a side wall along said epitaxial layer; a highly doped regionof said N conductivity type formed along said side wall of the firsttrench; and a drain plug in said first trench adjacent said highly dopedregion; an insulating layer extending along sidewalls of said conductivegate, over said conductive gate and over said drain region, saidinsulating layer comprising a first portion over said drain region and asecond portion over said drain plug, said second portion being thickerthan said first portion; and a source contact electrically connected tosaid source region and providing an electrical short between the sourceregion and the channel region, said source contact comprising a layer ofconductive material deposited over said insulating layer and in a secondtrench formed adjacent said source and channel regions and extendinginto said channel region.
 18. The device of claim 17, wherein said atleast one buffer region comprises first buffer region of said Pconductivity type formed between said substrate and said channel region,and a second buffer region of said N conductivity type formed betweensaid first buffer region and said substrate.
 19. The device of claim 17,further comprising a highly doped region of said P conductivity typeformed in said channel region proximate a bottom of said second trench.20. The device of claim 17, further comprising an edge terminationregion surrounding the active area of said transistor and separatingsaid transistor from an edge of a die having said transistor formedthereon, said edge termination region comprising a well region of thesecond conductivity type formed in said epitaxial layer, wherein saidlayer of conductive material extends beyond said well region and oversaid insulating layer; and wherein said drain plug is formed at orproximate to the edge of the die.
 21. A lateralmetal-oxide-semiconductor power transistor device comprising: asubstrate having a first conductivity type having a lightly dopedepitaxial layer thereon having an upper surface; source and drainregions of the first conductivity type formed in the epitaxial layerproximate the upper surface, said source and drain regions being spacedfrom one another and having a channel region of a second conductivitytype formed therebetween in said epitaxial layer, said channel regionextending under said source region; a conductive gate formed over a gatedielectric layer formed over said channel region and partiallyoverlapping said source and drain regions; at least one buffer layerhaving a dopant concentration equal to or greater than said channelregion formed between said channel region and said substrate; a draincontact electrically connecting said drain region to said substrate andspaced from said channel region comprising a highly doped verticalimplant region of said first conductivity type formed in said epitaxiallayer; a source contact electrically connected to said source region andproviding an electrical short between the source region and the channelregion; and an insulating layer formed between said conductive gate andsaid source contact.